| 2006-10 | Interconnect Delay Fault Test on Boards and SoCs with Multiple Clock Domains | 박성주 |
| 2008-06 | Interconnect Delay Fault Test on Boards and SoCs with Multiple Clock Domains | 박성주 |
| 2008-05 | Low Cost Scan Test for IEEE 1500-Based SoC | 박성주 |
| 2016-10 | Low Power Scan Chain Reordering Method with Limited Routing Congestion for Code-based Test Data Compression | 박성주 |
| 2008-05 | Low-cost scan test for IEEE-1500-Based SoC | 박성주 |
| 2021-11 | Master-Slave based test cost reduction method for DNN Accelerators | 박성주 |
| 2001-11 | A Microcode-based Memory BIST Implementing Modified March Algorithm | 박성주 |
| 2002-04 | Microcode-based memory BIST implementing modified march algorithms | 박성주 |
| 2002-04 | Microcode-Based Memory BIST Implementing Modified March Algorithms | 박성주 |
| 2011-04 | Multiple cell upsets tolerant content-addressable memory | 박성주 |
| 2014-02 | Multiple Series Diode Biosensors with PtSi/p/p++-Si lateral junctions | 박성주 |
| 2002-10 | A New Boundary Matching algorithm Based on Edge Detection | 박성주 |
| 2004-07 | A New Design of High Speed Parallel CRC Generator | 박성주 |
| 2000-03 | A NEW IEEE 1149.1 BOUNDARY SCAN DESIGN FOR THE DETECTION OF DELAY DEFECTS | 박성주 |
| 2004-10 | A New State Assignment Technique for Testing and Low Power | 박성주 |
| 2003-02 | A New State Assignment Technique for Testing and Low Power | 박성주 |
| 2004-06 | A New State Assignment Technique for Testing and Low Power | 박성주 |
| 2004-02 | A new synthesis technique of sequential circuits for low power and testing | 박성주 |
| 2001-11 | A New Wrapped Core Linking Module for SoC Testing | 박성주 |
| 2000-04 | NPSFs를 고려한 수정된 March 알고리즘 | 박성주 |
| 2000-01 | NPSFs를 고려한 수정된 March 알고리즘 | 박성주 |
| 2017-07 | On Diagnosing the Aging Level of Automotive Semiconductor Devices | 박성주 |
| 2010-07 | On-Chip Support for NoC-Based SoC Debugging | 박성주 |
| 2008-06 | Optimal SoC Test Interface for Wafer and Final Tests | 박성주 |
| 2000-08 | Optimal state assignment technique for partial scan designs | 박성주 |
| 2001-11 | P1500 compliant Microcode-based Memory BIST for Testing of Embedded Memory | 박성주 |
| 2006-10 | Parallel CRC Logic Optimization Algorithm for High Speed Communication Systems | 박성주 |
| 2009-11 | Parallel test method for NoC-based SoCs | 박성주 |
| 2000-05 | A Partial Scan Design by Unifying Structural Analysis and Testabilities | 박성주 |
| 2001-12 | A Partial Scan Design Unifying Structural Analysis and Testabilities | 박성주 |
