Optimal SoC Test Interface for Wafer and Final Tests
- Optimal SoC Test Interface for Wafer and Final Tests
- Issue Date
- 제9회 한국테스트학술대회, C-2
- The throughput of wafer testing can be significantly improved by
allowing multi-site test through the reduced pin count testing (RPCT).
Nonetheless, owing to the reduced number of test ports with the lengthy
test patterns serialized for the RPCT, the throughput of the final test is
even degraded. In this paper, an efficient RPCT for wafer test is
introduced for system-on-a-chips (SoC) with IEEE 1500 wrapped cores,
and then the RPCT is transformed to full pin test interface for the final
package test. A mathematically analyzed guideline is provided to adopt
the RPCT for SoCs embedding modules that require too lengthy scan
test patterns. Experiments show the effectiveness of our technique in
globally improving the test throughput with an unusual case where the
throughput was even degraded with the RPCT for wafer test.
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- COLLEGE OF COMPUTING[E] > COMPUTER SCIENCE(소프트웨어학부) > Articles
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