25 0

Parallel CRC Logic Optimization Algorithm for High Speed Communication Systems

Title
Parallel CRC Logic Optimization Algorithm for High Speed Communication Systems
Author
박성주
Issue Date
2006-10
Publisher
IEEE
Citation
2006 10th IEEE Singapore International Conference on Communication Systems, Article no. 4085745
Abstract
This paper presents a new optimization algorithm for designing parallel Cyclic Redundancy Check (CRC) circuits widely adopted to detect burst errors in high-speed communications. Our heuristic algorithm is focused on minimizing the logic level and finding XOR terms shared as many as possible. An Ethernet 32-bit CRC generator, which was designed and mapped to FPGA and a standard cell library, shows the superiority of our approach in reducing the delay and area overhead.
URI
https://ieeexplore.ieee.org/document/4085745http://repository.hanyang.ac.kr/handle/20.500.11754/108562
ISBN
978-142440411-7
DOI
10.1109/ICCS.2006.301450
Appears in Collections:
COLLEGE OF COMPUTING[E] > COMPUTER SCIENCE(소프트웨어학부) > Articles
Files in This Item:
There are no files associated with this item.
Export
RIS (EndNote)
XLS (Excel)
XML


qrcode

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

BROWSE