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Low Cost Scan Test for IEEE 1500-Based SoC

Title
Low Cost Scan Test for IEEE 1500-Based SoC
Author
박성주
Keywords
delay test; design-for-testability (DtT); IEEE 1500; reduced pin-count test (RPCT); system-on-a-chip (SoC)
Issue Date
2008-05
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, v. 57, No. 5, Page. 1071-1078
Abstract
In this paper, a reduced-pin-count-testing technique is presented to control the IEEE-1500 wrapper through the IEEE-1149.1 TAP for scan delay test. By using only the IEEE1149.1 TAP control pins as test-access pins and by embedding an on-chip test clock generator, low-cost automated test equipment (ATE) can be efficiently utilized to reduce testing costs. Experiments show the effectiveness of our technique in utilizing the ATE channels and scan delay testing.
URI
https://ieeexplore.ieee.org/abstract/document/4432930http://repository.hanyang.ac.kr/handle/20.500.11754/80374
ISSN
0018-9456
DOI
10.1109/TIM.2007.911699
Appears in Collections:
COLLEGE OF COMPUTING[E] > COMPUTER SCIENCE(소프트웨어학부) > Articles
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