A New Design of High Speed Parallel CRC Generator

Abstract

This paper presents an optimization algorithm and technique for designing parallel Cyclic Redundancy Check (CRC) circuit, which is most widely adopted for error detection. A new heuristic algorithm is developed to find as many shared terms as possible, thus eventually to minimize the number and level of the exclusive-or logic blocks in parallel CRC circuits. 16-bit and 32-bit CRC generators are designed with different types of Programmable Logic Devices, and it has been found that our new algorithm and architecture significantly reduce the delay