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Interconnect Delay Fault Test on Boards and SoCs with Multiple Clock Domains

Title
Interconnect Delay Fault Test on Boards and SoCs with Multiple Clock Domains
Author
박성주
Keywords
design for testability; system-on-chip; IEEE 1149.1; IEEE 1500; multiple clock domains
Issue Date
2008-06
Publisher
ELECTRONICS TELECOMMUNICATIONS RESEARCH INST
Citation
ETRI JOURNAL, v. 30, No. 3, Page. 403-411
Abstract
This paper introduces an interconnect delay fault test (IDFT) controller on boards and system-on-chips (SoCs) with IEEE 1149.1 and IEEE 1500 wrappers. By capturing the transition signals launched during one system clock, interconnect delay faults operated by different system clocks can be simultaneously tested with our technique. The proposed IDFT technique does not require any modification on boundary scan cells. Instead, a small number of logic gates needs to be plugged around the test access port controller. The IDFT controller is compatible with the IEEE 1149.1 and IEEE 1500 standards. The superiority of our approach is verified by implementation of the controller with benchmark SoCs with IEEE 1500 wrapped cores.
URI
https://onlinelibrary.wiley.com/doi/abs/10.4218/etrij.08.0107.0275http://repository.hanyang.ac.kr/handle/20.500.11754/104696
ISSN
1225-6463
DOI
10.4218/etrij.08.0107.0275
Appears in Collections:
COLLEGE OF COMPUTING[E] > COMPUTER SCIENCE(소프트웨어학부) > Articles
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