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Interconnect Delay Fault Test on Boards and SoCs with Multiple Clock Domains

Title
Interconnect Delay Fault Test on Boards and SoCs with Multiple Clock Domains
Author
박성주
Issue Date
2006-10
Publisher
IEEE
Citation
2006 IEEE International Test Conference, Article no. 4079310
Abstract
This paper introduces an efficient interconnect delay fault test (IDFT) controller on boards and SoCs with IEEE 1149.1 and IEEE 1500 wrappers. By capturing the transition signals launched during one system clock, interconnect delay faults operated by different system clocks can be effectively tested with our technique. The IDFT controller proposed does not require any modification on boundary scan cells, instead very simple logic needs to be plugged around the TAP controller. Complete compatibility with the IEEE 1149.1 and IEEE 1500 standards is preserved and the superiority of this approach is verified through design experiments. © 2006 IEEE.
URI
https://ieeexplore.ieee.org/document/4079310http://repository.hanyang.ac.kr/handle/20.500.11754/108626
ISSN
1089-3539
DOI
10.1109/TEST.2006.297632
Appears in Collections:
COLLEGE OF COMPUTING[E] > COMPUTER SCIENCE(소프트웨어학부) > Articles
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