| 2002-10 | A New Boundary Matching algorithm Based on Edge Detection | 박성주 |
| 2004-07 | A New Design of High Speed Parallel CRC Generator | 박성주 |
| 2000-03 | A NEW IEEE 1149.1 BOUNDARY SCAN DESIGN FOR THE DETECTION OF DELAY DEFECTS | 박성주 |
| 2004-10 | A New State Assignment Technique for Testing and Low Power | 박성주 |
| 2003-02 | A New State Assignment Technique for Testing and Low Power | 박성주 |
| 2004-06 | A New State Assignment Technique for Testing and Low Power | 박성주 |
| 2004-02 | A new synthesis technique of sequential circuits for low power and testing | 박성주 |
| 2001-11 | A New Wrapped Core Linking Module for SoC Testing | 박성주 |
| 2000-04 | NPSFs를 고려한 수정된 March 알고리즘 | 박성주 |
| 2000-01 | NPSFs를 고려한 수정된 March 알고리즘 | 박성주 |
| 2017-07 | On Diagnosing the Aging Level of Automotive Semiconductor Devices | 박성주 |
| 2010-07 | On-Chip Support for NoC-Based SoC Debugging | 박성주 |
| 2008-06 | Optimal SoC Test Interface for Wafer and Final Tests | 박성주 |
| 2000-08 | Optimal state assignment technique for partial scan designs | 박성주 |
| 2001-11 | P1500 compliant Microcode-based Memory BIST for Testing of Embedded Memory | 박성주 |
| 2006-10 | Parallel CRC Logic Optimization Algorithm for High Speed Communication Systems | 박성주 |
| 2009-11 | Parallel test method for NoC-based SoCs | 박성주 |
| 2000-05 | A Partial Scan Design by Unifying Structural Analysis and Testabilities | 박성주 |
| 2001-12 | A Partial Scan Design Unifying Structural Analysis and Testabilities | 박성주 |
| 2000-12 | PCI 버스 기반의 고속 병렬신호처리보드의 개발 | 박성주 |
| 2011-04 | Performance Improvement by Logic Sharing on Using Unused Spare Columns for Memory EC | 박성주 |
| 2004-10 | A Reconfigurable Test Access Mechanism for Embedded Core Test | 박성주 |
| 2011-08 | Redundancy TSV 연결 테스트를 위한 래퍼셀 설계 | 박성주 |
| 2014-01 | Reliability issues for automobile SoCs | 박성주 |
| 2021-08 | Reliable Test Architecture with Test Cost Reduction for Systolic based DNN accelerators | 박성주 |
| 2015-11 | SCAN-PUF: PUF Elements Selection Methods for Viable IC Identification | 박성주 |
| 2002-11 | A simple wrapped core linking module for SoC test access | 박성주 |
| 2002-11 | A Simple Wrapped Core Linking Module for SoC Test Access | 박성주 |
| 2016-10 | Test Access Mechanism for Automotive Chips through Vehicular Control Networks | 박성주 |
| 2021-07 | Test Architecture for Systolic Array of Edge-Based AI Accelerator | 박성주 |
