A NEW IEEE 1149.1 BOUNDARY SCAN DESIGN FOR THE DETECTION OF DELAY DEFECTS

Abstract

Delay defects on I/O pads, interconnections of a board, or interconnections among embedded cores cannot be tested with the current IEEE 1149.1 boundary scan design. This paper introduces a simple design technique which slightly modifies the TAP controller to test delay defects by postponing the UpdateDR with EXTEST instruction. Furthermore, 2log(N+2) interconnect test patterns are proposed for both static and delay testing.