A new synthesis technique of sequential circuits for low power and testing

Abstract

The state assignment for a finite state machine greatly affects the delay, area, power dissipation, and testabilities of the sequential circuits. In order to improve the testabilities and power consumption, a new state assignment technique based on m-block partition is introduced in this paper. By the m-block partition algorithm, the dependencies among groups of state variables are minimized and switching activity is further reduced by assigning the codes of the states in the same group considering the state transition probability among the states. In the sequel the length and number of feedback cycles are reduced with minimal switching activity on the state variables. It is inherently contradictory problem to optimize the testability and power consumption simultaneously, however our new state assignment technique is able to achieve high fault coverage with less number of scan flip-flops by reducing the number of feedback cycles while the power consumption is kept low upon the low switching activities among state variables. Experiment shows significant improvement in power dissipation with comparable testabilities for benchmark circuits.