A New Wrapped Core Linking Module for SoC Testing

Abstract

For a System-on-a-Chip(SoC) comprised of multiple IP cores with IEEE 1149.1 boundary scan design, various design techniques have been proposed to provide diverse test link configurations. In this paper, we present a new design of Wrapped Core Linking Module(WCLM) that enables systematic integration of 1149.1 JTAG'd cores and PI500 wrapped cores. The design preserves compatibility with standards and scalablity for hierarchical access.