A Reconfigurable Test Access Mechanism for Embedded Core Test

Abstract

For a System-on-a-Chip(SoC) comprised of multiple IP cores, various design techniques have been proposed to provide diverse test link configurations for wrapper and scan chains. In this paper, a simple test access mechanism is introduced, where scan chains are efficiently reconfigured. An SoC comprising of interactive and non-interactive mega-cores of various scan architectures can be effectively tested with this mechanism. Design experiments show that functionality, compatability, scalability, and area overhead of our technique are highly competitive to the current state-of art techniques.