Reliable Test Architecture with Test Cost Reduction for Systolic based DNN accelerators

Abstract

Deep Neural Network (DNN) accelerators are now ubiquitous. Extensive research is being directed at low power DNN accelerators for battery operated devices at the expense of a little drop in accuracy. These DNN accelerators have large number of registers resulting in larger scan chains, which results in larger test times and higher IR drop issues. Conventional full scan design-for-testability (DFT) approach may result in test overhead in terms of; area overhead, test time, test power, test pins. In this paper, a novel DFT solution is proposed to overcome these test overheads. The proposed test access mechanism (TAM) uses existing data paths to transport the test pattern data to all PEs and reduce the IR drop based noise in test responses, thus enhancing the validity of testing process. The proposed TAM is able to reduce peak power around 64% and test time of around 89% on average in comparison to conventional testing methodology. The proposed technique is also able to reduce test time around 35% and peak power to 59% against an industrial testing methodology for DNN accelerators.