2002-12 | A Genetic Algorithm for the Minimization of OPKFDDs | 박성주 |
2009-01 | Highly Compact Interconnect Test Patterns for Crosstalk and Static Faults | 박성주 |
2021-09 | Highly Efficient Test Architecture for Low Power AI Accelerators | 박성주 |
2007-11 | Hybrid Test Data Compression Technique for Low-power Scan Test Data | 박성주 |
2005-09 | Hybrid Test Data Compression Technique for SoC Scan Testing | 박성주 |
2015-02 | Hybrid Test Data Transportation Scheme for Advanced NoC-Based SoCs | 박성주 |
2006-10 | IEEE 1149.1 테스트 기능이 내장된 PCI/USB 통합 인터페이스 회로의 설계 | 박성주 |
2006-10 | IEEE 1149.1 테스트 기능이 내장된PCI/USB 통합 인터페이스 회로의 설계 | 박성주 |
2013-09 | IEEE 1149.7 표준 테스트 인터페이스를 사용한 핀 수 절감 테스트 기술 | 박성주 |
2008-02 | IEEE 1500 래퍼를 이용한 효과적인 AMBA 기반 시스템-온-칩 코아 테스트 | 박성주 |
2020-02 | An Improved LDPC ECC based on System Level Reprogramming for MLC NAND Flash | 박성주 |
2004-11 | InfiniBand/PCI-Express 4X Framer/Deframer 모듈 FPGA설계 | 박성주 |
2006-10 | Interconnect Delay Fault Test on Boards and SoCs with Multiple Clock Domains | 박성주 |
2008-06 | Interconnect Delay Fault Test on Boards and SoCs with Multiple Clock Domains | 박성주 |
2008-05 | Low Cost Scan Test for IEEE 1500-Based SoC | 박성주 |
2016-10 | Low Power Scan Chain Reordering Method with Limited Routing Congestion for Code-based Test Data Compression | 박성주 |
2008-05 | Low-cost scan test for IEEE-1500-Based SoC | 박성주 |
2021-11 | Master-Slave based test cost reduction method for DNN Accelerators | 박성주 |
2001-11 | A Microcode-based Memory BIST Implementing Modified March Algorithm | 박성주 |
2002-04 | Microcode-based memory BIST implementing modified march algorithms | 박성주 |
2002-04 | Microcode-Based Memory BIST Implementing Modified March Algorithms | 박성주 |
2011-04 | Multiple cell upsets tolerant content-addressable memory | 박성주 |
2014-02 | Multiple Series Diode Biosensors with PtSi/p/p++-Si lateral junctions | 박성주 |
2002-10 | A New Boundary Matching algorithm Based on Edge Detection | 박성주 |
2004-07 | A New Design of High Speed Parallel CRC Generator | 박성주 |
2000-03 | A NEW IEEE 1149.1 BOUNDARY SCAN DESIGN FOR THE DETECTION OF DELAY DEFECTS | 박성주 |
2004-10 | A New State Assignment Technique for Testing and Low Power | 박성주 |
2003-02 | A New State Assignment Technique for Testing and Low Power | 박성주 |
2004-06 | A New State Assignment Technique for Testing and Low Power | 박성주 |
2004-02 | A new synthesis technique of sequential circuits for low power and testing | 박성주 |