Highly Efficient Test Architecture for Low Power AI Accelerators

Abstract

Low power AI accelerators are being developed to support the battery-operated edge devices at a minimum expense of classification error. However, the testing of such large AI accelerators with traditional techniques is inefficient in achieving the required certifications for Autonomous Driving Assistant Systems (ISO 26262). ISO 26262 sets very stringent requirements on the testing time and fault coverage during diagnosability of faults leading to system level failures during in-field testing. This paper proposes a test architecture for low power AI accelerators by reusing the existing data paths for large AI accelerator arrays. As compared to the full scan-DFT, the proposed test architecture reduces the test time and peak test power, which enhances the reliability of the test responses. The proposed technique reduces (1) the switching power by 87%, (2) testing times by 72% on average for cases upto 32 × 32 and (3) the peak power by 59%. Further, there is an average reduction in area by 10% for the accelerator.