2014-06 | A 1.5-5.0 Gb/s clock and data recovery circuit with dual-PFD phase-rotating phase locked loop | 유창식 |
2014-06 | A 100-kS/s 8.3-ENOB 1.7-mu W Time-Domain Analog-to-Digital Converter | 유창식 |
2019-04 | A 12-Gb/s continuous-time linear equalizer with offset canceller | 유창식 |
2018-07 | A 12-Gb/s HDMI 2.1 quarter-rate transmitter in 28-nm bulk CMOS process | 유창식 |
2011-11 | A 20-MHz Bandwidth Continuous-Time Sigma-Delta Modulator With Jitter Immunity Improved Full Clock Period SCR (FSCR) DAC and High-Speed DWA | 유창식 |
2011-07 | A 2x2 MIMO Tri-Band Dual-Mode Direct-Conversion CMOS Transceiver for Worldwide WiMAX/WLAN Applications | 유창식 |
2012-11 | A 3.0-W Wireless Power Receiver Circuit with 75-% Overall Efficiency | 유창식 |
2019-07 | A 4-MHz Bandwidth Continuous-Time Sigma-Delta Modulator With Stochastic Quantizer and Digital Accumulator | 유창식 |
2015-08 | A 40-W Flyback Converter with Dual-Operation Modes for Improved Light Load Efficiency | 유창식 |
2015-06 | A 5.25-V-tolerant bidirectional I/O circuit in a 28-nm CMOS process | 유창식 |
2013-08 | A 6-Gb/s Differential Voltage Mode Driver with Independent Control of Output Impedance and Pre-Emphasis Level | 유창식 |
2020-05 | A 6-Gb/s Wireline Receiver With Intrapair Skew Compensation and Three-Tap Decision-Feedback Equalizer in 28-nm CMOS | 유창식 |
2015-10 | A 6-Gbps dual-mode digital clock and data recovery circuit in a 65-nm CMOS technology | 유창식 |
2015-04 | A 6-Gbps/lane receiver for a clock-forwarded link in 65-nm CMOS process | 유창식 |
2013-06 | A 6.0-W Bi-Directional DC-DC Converter for Wireless Power Transceiver in 0.35-μm BCDMOS | 유창식 |
2011-02 | Active Power Factor Correction (PFC) Circuit With Resistor-Free Zero-Current Detection | 유창식 |
2015-08 | An analog sigma-delta modulator with shared operational amplifier for low-power class-D audio amplifier | 유창식 |
2013-06 | An automatic load-adaptive switching frequency selection technique for improving the light-load efficiency of a buck converter | 유창식 |
2014-02 | A CCM/DCM Dual-Mode Synchronous Rectification Controller for a High-Efficiency Flyback Converter | 유창식 |
2013-10 | A Class-D Amplifier for a Digital Hearing Aid with 0.015% Total Harmonic Distortion Plus Noise | 유창식 |
2013-02 | A Class-D Amplifier With Pulse Code Modulated (PCM) Digital Input for Digital Hearing Aid | 유창식 |
2018-11 | Continuous-time linear equalizer with automatic boosting gain adaptation and input offset cancellation | 유창식 |
2018-08 | A Continuous-time Sigma-delta Modulator with Clock Jitter Tolerant Self-resetting Return-to-zero Feedback DAC | 유창식 |
2015-09 | Crosstalk cancelling voltage-mode driver for multi-Gbps parallel DRAM interface | 유창식 |
2018-10 | A Current-Mode Boost Converter with Wide Bandwidth Inductor Current Sensor | 유창식 |
2019-11 | A Current-Mode Hysteretic Buck Converter With Multiple-Reset RC-Based Inductor Current Sensor | 유창식 |
2014-05 | Data and edge decision feedback equalizer with ˃ 1.0-UI timing margin for both data and edge samples | 유창식 |
2011-07 | dB-선형적 특성을 가진 GPS 수신기를 위한 CMOS 가변 이득 증폭기 | 유창식 |
2014-12 | Digital Phase Locked Loop (DPLL) with Offset Dithered Bang-Bang Phase Detector (BBPD) for Bandwidth Control | 유창식 |
2017-07 | Duty-cycle and phase spacing error correction circuit for high-speed serial link | 유창식 |