A 12-Gb/s continuous-time linear equalizer with offset canceller
- Title
- A 12-Gb/s continuous-time linear equalizer with offset canceller
- Author
- 유창식
- Keywords
- Continuous-time linear equalizer (CTLE); offset cancellation; chopping; pulse width modulation (PWM); CMOS
- Issue Date
- 2019-04
- Publisher
- IEEK PUBLICATION CENTER
- Citation
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v. 19, NO 2, Page. 220-225
- Abstract
- A DC-offset of a continuous-time linear equalizer (CTLE) is cancelled by an analog offset canceller (OFC). The bandwidth (BW) of the OFC is designed to be 10-kHz not to affect the received signal integrity. The BW of the OFC set by an active-RC integrator is lowered by increasing the effective resistance through pulse width modulation (PWM). The input offset of the OFC itself is removed by employing chopping technique. The offset-cancelled CTLE is applied to a four-channel 12-Gb/s wireline receiver compliant with the high-definition multimedia interface (HDMI) version 2.1 standard. The 12-Gb/s wireline receiver has been implemented in a 28-nm CMOS process. The eye opening for the bit-error rate (BER) smaller than 10(-12) becomes larger than 0.26 unit-interval (U1) with the OFC while the BER is always larger than 10(-12) without the OFC.
- URI
- http://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE08007003&language=ko_KRhttps://repository.hanyang.ac.kr/handle/20.500.11754/110946
- ISSN
- 1598-1657; 2233-4866
- DOI
- 10.5573/JSTS.2019.19.2.220
- Appears in Collections:
- COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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