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A 6-Gb/s Wireline Receiver With Intrapair Skew Compensation and Three-Tap Decision-Feedback Equalizer in 28-nm CMOS

Title
A 6-Gb/s Wireline Receiver With Intrapair Skew Compensation and Three-Tap Decision-Feedback Equalizer in 28-nm CMOS
Author
유창식
Keywords
Clock and data recovery (CDR); CMOS; decision feedback equalizer (DFE); intrapair skew (IPS); wireline receiver
Issue Date
2020-05
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v. 28, no. 5, page. 1107-1117
Abstract
A receiver for a three-lane 6-Gb/s/lane serial link has been developed in 28-nm CMOS technology. It incorporates an intrapair skew compensator (IPSC) and a three-tap decision feedback equalizer (DFE). The IPSC removes the IPS in analog front end by adding differential and common-mode signals of a differential pair. The three-tap DFE is realized with clock and data recovery (CDR) circuit with minimum hardware complexity. The receiver consumes 31.0 mW/lane at 6 Gb/s/lane and occupies an active area of 0.08 mm(2).
URI
https://ieeexplore.ieee.org/document/8999809https://repository.hanyang.ac.kr/handle/20.500.11754/166705
ISSN
1063-8210; 1557-9999
DOI
10.1109/TVLSI.2020.2971558
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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