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A 100-kS/s 8.3-ENOB 1.7-mu W Time-Domain Analog-to-Digital Converter

Title
A 100-kS/s 8.3-ENOB 1.7-mu W Time-Domain Analog-to-Digital Converter
Other Titles
s 8.3-ENOB 1.7-mu W Time-Domain Analog-to-Digital Converter
Author
유창식
Keywords
Analog-to-digital converter (ADC); CMOS; delay line; successive approximation register (SAR); time-domain comparator
Issue Date
2014-06
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 445 HOES LANE, PISCATAWAY, NJ 08855-4141 USA
Citation
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 권: 61, 호: 6, 페이지: 408-412
Abstract
A 100-kS/s time-domain analog-to-digital converter (TDADC) with successive approximation register architecture provides 8.3 effective bits. The time-domain comparator of the TDADC is realized with only one delay line consisting of a digitally controlled delay line and a voltage-controlled delay line. Therefore, the linearity degradation due to the mismatch between multiple delay lines can be avoided. The TDADC has been implemented in a 0.11-mu m CMOS process with a 0.127-mm(2) active silicon area. The TDADC consumes 1.7 mu W from a 0.6-V supply voltage.
URI
http://ieeexplore.ieee.org/abstract/document/6805213/http://hdl.handle.net/20.500.11754/52088
ISSN
1549-7747; 1558-3791
DOI
10.1109/TCSII.2014.2319973
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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