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A 6-Gbps dual-mode digital clock and data recovery circuit in a 65-nm CMOS technology

Title
A 6-Gbps dual-mode digital clock and data recovery circuit in a 65-nm CMOS technology
Author
유창식
Keywords
Clock and data recovery (CDR); Phase locked loop (PLL); Digitally-controlled oscillator (DCO)
Issue Date
2015-10
Publisher
SPRINGER
Citation
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, v. 85, NO 1, Page. 209-215
Abstract
A 6-Gbps dual-mode digital clock and data recovery (CDR) circuit for both the mesochronous clocking system and the plesiochronous clocking system has been developed. Fabricated in a 65-nm CMOS technology, the prototype consumes 25.2 and 22.8-mW from 1.2-V supply and root-mean-square jitter of the recovered clock was measured to be 7.2 and 8.5-ps for 6-Gbps mesochronous system and plesiochronous system, respectively. For both operation modes, less than 10(-12) bit-error-rate was achieved with 2(7)-1 pseudo-random binary sequence pattern and active area of the implemented CDR circuit is 0.025-mm(2).
URI
https://link.springer.com/article/10.1007%2Fs10470-015-0613-0http://hdl.handle.net/20.500.11754/28397
ISSN
0925-1030; 1573-1979
DOI
10.1007/s10470-015-0613-0
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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