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A 4-MHz Bandwidth Continuous-Time Sigma-Delta Modulator With Stochastic Quantizer and Digital Accumulator

Title
A 4-MHz Bandwidth Continuous-Time Sigma-Delta Modulator With Stochastic Quantizer and Digital Accumulator
Author
유창식
Keywords
Sigma-delta modulator (SDM); continuous-time (CT); analog-to-digital converter (ADC); stochastic quantizer; input offset; CMOS
Issue Date
2019-07
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v. 66, no. 7, Page. 1124-1128
Abstract
A 4-MHz bandwidth continuous-time (CT) sigma-delta modulator (SDM) is described. The CT-SDM employs a stochastic quantizer consisting of 63 comparators whose random input offset provides linear multi-bit quantization. The output of the stochastic quantizer is accumulated by a digital accumulator before feeding it back to the input of the loop filter of the CT-SDM, which greatly improves the linearity of the stochastic quantization. The CT-SDM implemented in a 65-nm CMOS technology shows the peak signal-to-noise+distortion ratio of 72.5-dB while consuming 3.6-mW from a 0.9-V supply.
URI
https://ieeexplore.ieee.org/document/8532284https://repository.hanyang.ac.kr/handle/20.500.11754/152323
ISSN
1549-7747; 1558-3791
DOI
10.1109/TCSII.2018.2880912
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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