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Duty-cycle and phase spacing error correction circuit for high-speed serial link

Title
Duty-cycle and phase spacing error correction circuit for high-speed serial link
Author
유창식
Keywords
duty-cycle; phase spacing; analogue-to-digital converter (ADC); CMOS; deterministic jitter
Issue Date
2017-07
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Citation
IEICE ELECTRONICS EXPRESS, v. 14, no. 12, Article no. 20170497
Abstract
Duty cycle and phase spacing of multi-phase clock are converted to an analog voltage by low-pass filtering a clock pulse and quantized by a low-power analog-to-digital converter (ADC). The pull-up and pull-down strengths and the delay of clock buffer are controlled till the duty cycle and phase spacing measured by the ADC become equal to desired values. A prototype has been implemented in a 28-nm CMOS process for a 12-Gbps serial link transceiver and occupies only 0.0014-mm(2). Experimental results show the deterministic jitter decreases from 8.12-ps to 0.91-ps by the proposed duty cycle and phase spacing error correction technique. While operating with a 1.0-V supply, the additional power consumed for the duty cycle and phase spacing error correction is only 76-mu W.
URI
https://www.jstage.jst.go.jp/article/elex/14/12/14_14.20170497/_articlehttps://repository.hanyang.ac.kr/handle/20.500.11754/114962
ISSN
1349-2543
DOI
10.1587/elex.14.20170497
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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