| 2006-11 | Efficient Interconnect Test Patterns for Crosstalk and Static Faults | 백상현 |
| 2020-05 | Energy straggling and an experimental investigation of Bragg's rule for Am-241 alpha particles in air and its constituents | 백상현 |
| 2017-01 | Evaluation of SEU Performance of 28-nm FDSOI Flip-Flop Designs | 백상현 |
| 2019-08 | Experimental Exploitation of Random and Deterministic Data Patterns for Stringent DDR4 I/O Timing Margins | 백상현 |
| 2016-02 | Experiments and root cause analysis for active-precharge hammering fault in DDR3 SDRAM under 3 x nm technology | 백상현 |
| 2021-10 | Exploitations of Multiple Rows Hammering and Retention Time Interactions in DRAM Using X-Ray Radiation | 백상현 |
| 2020-10 | Failure Analysis of Galaxy S7 Edge Smartphone Using Neutron Radiation | 백상현 |
| 2018-09 | Failure signature analysis of power-opens in DDR3 SDRAMs | 백상현 |
| 2021-09 | Fault Coverage Re-Evaluation of Memory Test Algorithms With Physical Memory Characteristics | 백상현 |
| 2020-07 | FBGA solder ball defect e ff ect on DDR4 data signal rise time and ISI measured by loading the data line with a capacitor | 백상현 |
| 2020-11 | FBGA solder ball defect effect on DDR4 data signal rise time and ISI measured by loading the data line with a capacitor | 백상현 |
| 2012-12 | Hybrid Partitioned SRAM-Based Ternary Content Addressable Memory | 백상현 |
| 2008-12 | Hysteresis 버퍼를 이용한 AC 커플링 커패시터 테스트 | 백상현 |
| 2015-04 | Logic soft error study with 800-MHz DDR3 SDRAMs in 3x nm using proton and neutron beams | 백상현 |
| 2008-03 | Low Power Configuration Strategy of TCAM Lookup | 백상현 |
| 2008-03 | Low power configuration strategy of TCAM lookup table | 백상현 |
| 2008-07 | Low Power Ternary Content-Addressable Memories (TCAM) Design Using Segmented Match-Line | 백상현 |
| 2008-07 | Low-Power Ternary Content-Addressable Memory Design Using a Segmented Match Line | 백상현 |
| 2013-04 | Memory Reliability Analysis for Multiple Block Effect of Soft Errors | 백상현 |
| 2010-04 | Minimizing Soft Errors in TCAM Devices: A Probabilistic Approach to Determining Scrubbing Intervals | 백상현 |
| 2011-10 | Mitigating the Effects of Large Multiple Cell Upsets (MCUs) in Memories | 백상현 |
| 2018-08 | Modeling and analysis of single-event transient sensitivity of a 65 nm clock tree | 백상현 |
| 2011-04 | Multiple cell upsets tolerant content-addressable memory | 백상현 |
| 2014-10 | Novel Error Detection Scheme With the Harmonious Use of Parity Codes, Well-Taps, and Interleaving Distance | 백상현 |
| 2009-08 | Null Detector Circuit Design Scheme for Detecting Defective AC-Coupled Capacitors in Differential Signaling | 백상현 |
| 2010-06 | Optimizing Scrubbing Sequences for Advanced Computer Memories | 백상현 |
| 2010-08 | Protection of Memories Suffering MCUs Through the Selection of the Optimal Interleaving Distance | 백상현 |
| 2022-08 | Quantification of Substrate Current Caused by an Individual Trap at Different Locations and Energies, Prevailing on Si/SiO2 Interface or Si Substrate of n-MOSFETs | 백상현 |
| 2017-05 | A Quatro-Based 65-nm Flip-Flop Circuit for Soft-Error Resilience | 백상현 |
| 2019-09 | Radiation Reliability Benefit of Area-Optimized Interleaved Flip-Flop Layout in 28 nm Technology | 백상현 |
