IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v. 25, No. 11, Page. 2605-2608
Abstract
This paper introduces effective test patterns for system-on-chip and board interconnects. Initially, 6n patterns are introduced to completely detect and diagnose both static and crosstalk faults, where n is the total number of interconnect nets. Then, more economic 4n+1 patterns are described to test the crosstalk faults for the interconnect nets separated within a certain distance.