Experimental Exploitation of Random and Deterministic Data Patterns for Stringent DDR4 I/O Timing Margins
- Title
- Experimental Exploitation of Random and Deterministic Data Patterns for Stringent DDR4 I/O Timing Margins
- Author
- 백상현
- Keywords
- Programmable memory built-In selftest (PMBIST) margin test; DDR4 I/O timing margins; pseudo-random binary sequence(PRBS); interconnect fault model; fault-critical-random-94 (FCR-94) data pattern (DP) set
- Issue Date
- 2019-08
- Publisher
- 대한전자공학회
- Citation
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v. 19, No. 4, Page. 388-395
- Abstract
- In this paper, I/O timing margins are experimentally measured by DQS groups, for a DDR4 RDIMM with 2133 Mbps data rate, to study the margin effects of the special combination and sequence of random and fault-based deterministic data patterns. The most effective 94 data patterns are newly developed after experimentally investigating three test patterns factors, which consist of test algorithms, address directions, and data patterns; the most influential factor was data patterns, which resulted in the average margin reduction of 15.2%. The maximum of 11.8% margin was reduced by the proposed 94 patterns (in comparison to 28-bit PRBS pattern), which was from both selected PRBS and fault-based deterministic data patterns.
- URI
- http://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE08767118https://repository.hanyang.ac.kr/handle/20.500.11754/121950
- ISSN
- 1598-1657; 2233-4866
- DOI
- 10.5573/JSTS.2019.19.4.388
- Appears in Collections:
- COLLEGE OF ENGINEERING SCIENCES[E](공학대학) > ELECTRICAL ENGINEERING(전자공학부) > Articles
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