| 2012-12 | Vertically Partitioned SRAM-Based Ternary Content Addressable Memory | 백상현 |
| 2012-12 | Hybrid Partitioned SRAM-Based Ternary Content Addressable Memory | 백상현 |
| 2012-12 | Characterizing the Capacitive Crosstalk in SRAM Cells Using Negative Bit-Line Voltage Stress | 백상현 |
| 2013-04 | Memory Reliability Analysis for Multiple Block Effect of Soft Errors | 백상현 |
| 2013-11 | Soft error tolerant Content Addressable Memories (CAMs) using error detection codes and duplication | 백상현 |
| 2014-08 | An Efficient Multiple Cell Upsets Tolerant Content-Addressable Memory | 백상현 |
| 2014-10 | Novel Error Detection Scheme With the Harmonious Use of Parity Codes, Well-Taps, and Interleaving Distance | 백상현 |
| 2011-06 | Designing ad-hoc scrubbing sequences to improve memory reliability against soft errors | 백상현 |
| 2014-11 | Single Event Resilient Dynamic Logic Designs | 백상현 |
| 2015-04 | An SEU-Tolerant DICE Latch Design With Feedback Transistors | 백상현 |
| 2015-04 | Stuck Bits Study in DDR3 SDRAMs Using 45-MeV Proton Beam | 백상현 |
| 2017-07 | BPPT - Bulk potential protection technique for hardened sequentials | 백상현 |
| 2015-02 | Active-precharge hammering on a row induced failure in DDR3 SDRAMs under 3× nm technology | 백상현 |
| 2022-05 | Divulge of Root Cause Failure in Individual Cells of 2x nm Technology DDR4 DRAM at Operating Temperature | 백상현 |
| 2022-08 | Quantification of Substrate Current Caused by an Individual Trap at Different Locations and Energies, Prevailing on Si/SiO2 Interface or Si Substrate of n-MOSFETs | 백상현 |
| 2023-01 | DDR4 Ball Grid Array Package Intermittent Fracture Effect on Signal Integrity | 백상현 |
| 2023-01 | Temperature Estimation of HBM2 Channels with Tail Distribution of Retention Errors in FPGA-HBM2 Platform | 백상현 |
| 2015-04 | Logic soft error study with 800-MHz DDR3 SDRAMs in 3x nm using proton and neutron beams | 백상현 |
| 2020-11 | FBGA solder ball defect effect on DDR4 data signal rise time and ISI measured by loading the data line with a capacitor | 백상현 |
| 2007-02 | 99㏈의 DR를 갖는단일-비트 4차 고성능 델타-시그마 모듈레이터 설계 | 노정진 |
