| 2017-07 | BPPT - Bulk potential protection technique for hardened sequentials | 백상현 |
| 2017-07 | BPPT–Bulk Potential Protection Technique for Hardened Sequentials | 백상현 |
| 2005-09 | Built-In Null Detector Design For AC-Coupled Differential Receive Buffer | 백상현 |
| 2012-12 | Characterizing the Capacitive Crosstalk in SRAM Cells Using Negative Bit-Line Voltage Stress | 백상현 |
| 2012-09 | Comparative study of MC-50 and ANITA neutron beams by using 55 nm SRAM | 백상현 |
| 2019-08 | Correctable and uncorrectable errors using large scale DRAM DIMMs in replacement network servers | 백상현 |
| 2023-01 | DDR4 Ball Grid Array Package Intermittent Fracture Effect on Signal Integrity | 백상현 |
| 2023-01-23 | DDR4 Ball Grid Array Package Intermittent Fracture Effect on Signal Integrity | 백상현 |
| 2021-04 | DDR4 BER Degradation Due to Crack in FBGA Package Solder Ball | 백상현 |
| 2021-04 | DDR4 Data Channel Failure Due to DC Offset Caused by Intermittent Solder Ball Fracture in FBGA Package | 백상현 |
| 2007-12 | Delay Fault Coverage Enhancement by Partial Clocking For Low Power Designs with Heavily Gated Clocks | 백상현 |
| 2007-12 | Delay fault coverage enhancement by partial clocking for low-power designs with heavily gated clocks | 백상현 |
| 2011-03 | Design method of NOR-type comparison circuit in CAM with ground bounce noise considerations | 백상현 |
| 2011-06 | Designing ad-hoc scrubbing sequences to improve memory reliability against soft errors | 백상현 |
| 2022-05 | Divulge of Root Cause Failure in Individual Cells of 2x nm Technology DDR4 DRAM at Operating Temperature | 백상현 |
| 2011-07 | DRAM failure cases under hot-carrier injection | 백상현 |
| 2006-11 | Efficient Interconnect Test Patterns for Crosstalk and Static Faults | 백상현 |
| 2020-05 | Energy straggling and an experimental investigation of Bragg's rule for Am-241 alpha particles in air and its constituents | 백상현 |
| 2017-01 | Evaluation of SEU Performance of 28-nm FDSOI Flip-Flop Designs | 백상현 |
| 2019-08 | Experimental Exploitation of Random and Deterministic Data Patterns for Stringent DDR4 I/O Timing Margins | 백상현 |
