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BPPT–Bulk Potential Protection Technique for Hardened Sequentials

Title
BPPT–Bulk Potential Protection Technique for Hardened Sequentials
Author
백상현
Keywords
single events; single event transient; single event upset; hardening; pass transistors; LET; SER
Issue Date
2017-07
Publisher
IEEE
Citation
2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS), Page. 28-32
Abstract
In this paper, we present a method for hardening memory and sequential cells against soft errors. The effect of the ionizing particle on the bulk potential is exploited to prevent the induced SET from propagating in the circuit. The proposed method requires a minimum number of extra transistors. The solution is applied to D Flip-Flop design, and alpha and heavy-ions test results are presented.
URI
https://ieeexplore.ieee.org/document/8046194https://repository.hanyang.ac.kr/handle/20.500.11754/103490
ISBN
978-1-5386-0352-9
ISSN
1942-9401
DOI
10.1109/IOLTS.2017.8046194
Appears in Collections:
COLLEGE OF ENGINEERING SCIENCES[E](공학대학) > ELECTRICAL ENGINEERING(전자공학부) > Articles
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