Power bumps and through-silicon-vias placement with optimised power mesh structure for power delivery network in three-dimensional-integrated circuits
- Title
- Power bumps and through-silicon-vias placement with optimised power mesh structure for power delivery network in three-dimensional-integrated circuits
- Author
- 정정화
- Keywords
- 3D ICS
- Issue Date
- 2013-01
- Publisher
- IET
- Citation
- IET Computers and Digital Techniques, 2013, 7(1), p.11-20
- Abstract
- Three-dimensional-integrated circuits (3D-ICs) bring new issues for power delivery network design because of larger current density and more complicated power delivery paths compared to 2D-IC. The power delivery network consists of power bumps, through-silicon-vias (TSVs), and power wires. IR-drop at each node varies with the number and position of power bumps and TSVs. These three power resources affect IR-drop of 3D-ICs. In this study, the authors propose power delivery network design methodology to optimise power resources wherease IR-drop constraint is satisfied. The simulation results show that the proposed method minimises the number of power bumps and TSVs compared to the conventional method.
- URI
- http://digital-library.theiet.org/content/journals/10.1049/iet-cdt.2012.0047https://repository.hanyang.ac.kr/handle/20.500.11754/69689
- ISSN
- 1751-8601
- DOI
- 10.1049/iet-cdt.2012.0047
- Appears in Collections:
- COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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