Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 정정화 | - |
dc.date.accessioned | 2018-04-19T10:05:22Z | - |
dc.date.available | 2018-04-19T10:05:22Z | - |
dc.date.issued | 2013-01 | - |
dc.identifier.citation | IET Computers and Digital Techniques, 2013, 7(1), p.11-20 | en_US |
dc.identifier.issn | 1751-8601 | - |
dc.identifier.uri | http://digital-library.theiet.org/content/journals/10.1049/iet-cdt.2012.0047 | - |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/69689 | - |
dc.description.abstract | Three-dimensional-integrated circuits (3D-ICs) bring new issues for power delivery network design because of larger current density and more complicated power delivery paths compared to 2D-IC. The power delivery network consists of power bumps, through-silicon-vias (TSVs), and power wires. IR-drop at each node varies with the number and position of power bumps and TSVs. These three power resources affect IR-drop of 3D-ICs. In this study, the authors propose power delivery network design methodology to optimise power resources wherease IR-drop constraint is satisfied. The simulation results show that the proposed method minimises the number of power bumps and TSVs compared to the conventional method. | en_US |
dc.language.iso | en | en_US |
dc.publisher | IET | en_US |
dc.subject | 3D ICS | en_US |
dc.title | Power bumps and through-silicon-vias placement with optimised power mesh structure for power delivery network in three-dimensional-integrated circuits | en_US |
dc.type | Article | en_US |
dc.relation.no | 1 | - |
dc.relation.volume | 7 | - |
dc.identifier.doi | 10.1049/iet-cdt.2012.0047 | - |
dc.relation.page | 11-20 | - |
dc.relation.journal | IET COMPUTERS AND DIGITAL TECHNIQUES | - |
dc.contributor.googleauthor | Jang, C. | - |
dc.contributor.googleauthor | Kim, J. | - |
dc.contributor.googleauthor | Ahn, B. | - |
dc.contributor.googleauthor | Chong, J. | - |
dc.relation.code | 2013003617 | - |
dc.sector.campus | S | - |
dc.sector.daehak | COLLEGE OF ENGINEERING[S] | - |
dc.sector.department | DEPARTMENT OF ELECTRONIC ENGINEERING | - |
dc.identifier.pid | jchong | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.