A 65 nm Temporally Hardened Flip-Flop Circuit
- Title
- A 65 nm Temporally Hardened Flip-Flop Circuit
- Author
- 백상현
- Keywords
- Flip-flop; SET; SEU; temporal hardening; CMOS TECHNOLOGY; HEAVY-ION; GUARD-GATES; DESIGN; UPSET; SENSITIVITY; PERFORMANCE; MECHANISMS; SRAMS; POWER
- Issue Date
- 2016-09
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Citation
- IEEE TRANSACTIONS ON NUCLEAR SCIENCE, v. 63, No. 6, Page. 2934-2940
- Abstract
- A guard-gate based flip-flop circuit temporally hardened against single-event effects is presented in this paper. Compared to several existed techniques, the organization of components inside the proposed design allows the improved performance- only one tau (the maximum width of a single-event transient (SET) to tolerate) is added into the setup time. A previously reported low-power delay element is applied, which helps make the proposed design power-efficient. The proposed design was implemented in a 65 nm CMOS bulk technology. Alpha and heavy-ions radiation experiments were performed to characterize its soft-error rates. Experimental results show that the proposed design presents no error with LETs up to 37.3 MeV-cm(2)/mg. Simulation results from the TFIT further validate the experimental results.
- URI
- https://ieeexplore.ieee.org/abstract/document/7565582/https://repository.hanyang.ac.kr/handle/20.500.11754/69321
- ISSN
- 0018-9499; 1558-1578
- DOI
- 10.1109/TNS.2016.2608911
- Appears in Collections:
- COLLEGE OF ENGINEERING SCIENCES[E](공학대학) > ELECTRICAL ENGINEERING(전자공학부) > Articles
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