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COLLEGE OF ENGINEERING[S](공과대학)
ELECTRONIC ENGINEERING(융합전자공학부)
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2017-05
HMC-MAC_Processing-in Memory Architecture for Multiply-Accumulate Operations with Hybrid Memory Cube
정기석
2017-04
Self-Adaptive Termination Check of Min-Sum Algorithm for LDPC Decoders Using the First Two Minima
정기석
2017-05
Simplified 2-Dimensional Scaled Min-Sum Algorithm for LDPC Decoder
정기석
2017-01
CasHMC: A Cycle-Accurate Simulator for Hybrid Memory Cube
정기석
2017-10
Low Power and High Performance Level-up Shifters for Mobile Devices with Multi-V-DD
정기석
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LDPC decoder
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adaptive min-sum decoding
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error correction codes
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Error-correction code
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Level shifter
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Low-density parity-check code
1
Low-density parity-check codes
1
Memory control and access
1
memory design
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Memory structures
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