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HMC-MAC_Processing-in Memory Architecture for Multiply-Accumulate Operations with Hybrid Memory Cube

Title
HMC-MAC_Processing-in Memory Architecture for Multiply-Accumulate Operations with Hybrid Memory Cube
Author
정기석
Keywords
Memory structures; memory used as logic; multiple data stream srchitectures; parallel processing
Issue Date
2017-05
Publisher
IEEE COMPUTER SOC
Citation
IEEE COMPUTER ARCHITECTURE LETTERS, v. 17, no. 1, page. 5-8
Abstract
Many studies focus on implementing processing-in memory (PIM) on the logic die of the hybrid memory cube (HMC) architecture. The multiply-accumulate (MAC) operation is heavily used in digital signal processing (DSP) systems. In this paper, a novel PIM architecture called HMC-MAC that implements the MAC operation in the HMC is proposed. The vault controllers of the conventional HMC are working independently to maximize the parallelism, and HMC-MAC is based on the conventional HMC without modifying the architecture much. Therefore, a large number of MAC operations can be processed in parallel. In HMC-MAC, the MAC operation can be carried out simultaneously with as much as 128 KB data. The correctness on HMC-MAC is verified by simulations, and its performance is better than the conventional CPU-based MAC operation when the MAC operation is consecutively executed at least six times
URI
https://ieeexplore.ieee.org/document/7917248https://repository.hanyang.ac.kr/handle/20.500.11754/114110
ISSN
1556-6056; 1556-6064
DOI
10.1109/LCA.2017.2700298
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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