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CasHMC: A Cycle-Accurate Simulator for Hybrid Memory Cube

Title
CasHMC: A Cycle-Accurate Simulator for Hybrid Memory Cube
Author
정기석
Keywords
Memory control and access; memory design; modeling of computer architecture; simulation
Issue Date
2017-01
Publisher
IEEE COMPUTER SOC
Citation
IEEE COMPUTER ARCHITECTURE LETTERS, v. 16, no. 1, page. 10-13
Abstract
3D-stacked DRAM has been actively studied to overcome the limits of conventional DRAM. The Hybrid Memory Cube (HMC) is a type of 3D-stacked DRAM that has drawn great attention because of its usability for server systems and processing-in-memory (PIM) architecture. Since HMC is not directly stacked on the processor die where the central processing units (CPUs) and graphic processing units (GPUs) are integrated, HMC has to be linked to other processor components through high speed serial links. Therefore, the communication bandwidth and latency should be carefully estimated to evaluate the performance of HMC. However, most existing HMC simulators employ only simple HMC modeling. In this paper, we propose a cycle-accurate simulator for hybrid memory cube called CasHMC. It provides a cycle-by-cycle simulation of every module in an HMC and generates analysis results including a bandwidth graph and statistical data. Furthermore, CasHMC is implemented in C++ as a single wrapped object that includes an HMC controller, communication links, and HMC memory. Instantiating this single wrapped object facilitates simultaneous simulation in parallel with other simulators that generate memory access patterns such as a processor simulator or a memory trace generator.
URI
https://ieeexplore.ieee.org/document/7544479https://repository.hanyang.ac.kr/handle/20.500.11754/112328
ISSN
1556-6056; 1556-6064
DOI
10.1109/LCA.2016.2600601
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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