디커플링 방법을 이용한 RC-Coupled 배선의 해석적 지연시간 예측 모델

Abstract

Timing delays due to VLSI circuit interconnects strongly depend on neighbor line switching patterns as well as input transition time. Considering both the input transition and input switching pattern, a new analytical timing delay model is developed by using the decoupling technique of transfer multicoupled lines into an effective single line. The analytical timing delay model can determine the timing delay of multi-coupled lines accurately as well as rapidly. It is verified by using DSMTechnology ( 0.1µm /low-k copper-based process) that the model has excellent agreement with the results of SPICE simulation.