STT-MRAM Read-circuit with Improved Offset Cancellation
- Title
- STT-MRAM Read-circuit with Improved Offset Cancellation
- Author
- 박상규
- Keywords
- STT-MRAM; read-circuit; offset cancellation; sensing margin
- Issue Date
- 2017-06
- Publisher
- IEEK PUBLICATION CENTER
- Citation
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v. 17, no. 3, page. 347-353
- Abstract
- We present a STT-MRAM read-circuit which mitigates the performance degradation caused by offsets from device mismatches. In the circuit, a single current source supplies read-current to both the data and the reference cells sequentially eliminating potential mismatches. Furthermore, an offset-free pre-amplification using a capacitor storing the mismatch information is employed to lessen the effect of the comparator offset. The proposed circuit was implemented using a 130-nm CMOS technology and Monte Carlo simulations of the circuit demonstrate its effectiveness in suppressing the effect of device mismatch.
- URI
- http://koreascience.or.kr/article/JAKO201719558339580.pagehttps://repository.hanyang.ac.kr/handle/20.500.11754/114277
- ISSN
- 1598-1657; 2233-4866
- DOI
- 10.5573/JSTS.2017.17.3.347
- Appears in Collections:
- COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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