Interconnect test; crosstalk faults; static faults; test pattern
Issue Date
2008-06
Publisher
한국반도체테스트협회
Citation
제9회 한국테스트학술대회, A-1
Abstract
In this paper, we present efficient test patterns for the crosstalk–induced
faults on System-on-a-Chip and board level interconnects considering
actual effective aggressors to minimize the pattern size. All static faults
also can be detected. The proposed method achieved the significant
reduction of the number of test patterns than prior works, while
preserving 100% fault coverage. We are in the process of extending the
proposed technique to built-in-self test logics.