전력 Through-Silicon-Via를 최적화하는 3D-IC의 전력 공급 네트워크 설계

Abstract

3D-ICs have many problems for power delivery network design due to larger supply currents and longer power delivery paths compared to 2D-ICs. The power delivery network is composed of power TSVs and power supply noise is changed extremelyby the number and location of power TSVs. So, it is important to optimize the power TSVs while power supply noise constraint is satisfied. In this paper, the power Through-Silicon-Via (TSV) optimization for power delivery network design of 3D-IC is proposed.