Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 정정화 | - |
dc.date.accessioned | 2018-04-15T04:35:11Z | - |
dc.date.available | 2018-04-15T04:35:11Z | - |
dc.date.issued | 2011-06 | - |
dc.identifier.citation | 대한전자공학회 학술대회 논문집, Vol.2011 No.6 [2011], 624-626(3쪽) | en_US |
dc.identifier.uri | http://www.dbpia.co.kr/Journal/ArticleDetail/NODE02336723 | - |
dc.identifier.uri | http://hdl.handle.net/20.500.11754/66444 | - |
dc.description.abstract | 3D-ICs have many problems for power delivery network design due to larger supply currents and longer power delivery paths compared to 2D-ICs. The power delivery network is composed of power TSVs and power supply noise is changed extremelyby the number and location of power TSVs. So, it is important to optimize the power TSVs while power supply noise constraint is satisfied. In this paper, the power Through-Silicon-Via (TSV) optimization for power delivery network design of 3D-IC is proposed. | en_US |
dc.language.iso | ko_KR | en_US |
dc.publisher | 대한전자공학회 | en_US |
dc.title | 전력 Through-Silicon-Via를 최적화하는 3D-IC의 전력 공급 네트워크 설계 | en_US |
dc.title.alternative | A Power Through-Silicon-Via Optimization for Power Delivery Network Design of 3D-IC | en_US |
dc.type | Article | en_US |
dc.relation.page | - | - |
dc.contributor.googleauthor | 이봉기 | - |
dc.contributor.googleauthor | 정정화 | - |
dc.contributor.googleauthor | Lee, Bong-Ki | - |
dc.contributor.googleauthor | Chong, Jong-Wha | - |
dc.sector.campus | S | - |
dc.sector.daehak | COLLEGE OF ENGINEERING[S] | - |
dc.sector.department | DEPARTMENT OF ELECTRONIC ENGINEERING | - |
dc.identifier.pid | jchong | - |
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