Repository at Hanyang UniversityCOLLEGE OF ENGINEERING[S](공과대학)ELECTRONIC ENGINEERING(융합전자공학부)Articles

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dc.contributor.author정정화-
dc.date.accessioned2018-04-15T04:35:11Z-
dc.date.available2018-04-15T04:35:11Z-
dc.date.issued2011-06-
dc.identifier.citation대한전자공학회 학술대회 논문집, Vol.2011 No.6 [2011], 624-626(3쪽)en_US
dc.identifier.urihttp://www.dbpia.co.kr/Journal/ArticleDetail/NODE02336723-
dc.identifier.urihttp://hdl.handle.net/20.500.11754/66444-
dc.description.abstract3D-ICs have many problems for power delivery network design due to larger supply currents and longer power delivery paths compared to 2D-ICs. The power delivery network is composed of power TSVs and power supply noise is changed extremelyby the number and location of power TSVs. So, it is important to optimize the power TSVs while power supply noise constraint is satisfied. In this paper, the power Through-Silicon-Via (TSV) optimization for power delivery network design of 3D-IC is proposed.en_US
dc.language.isoko_KRen_US
dc.publisher대한전자공학회en_US
dc.title전력 Through-Silicon-Via를 최적화하는 3D-IC의 전력 공급 네트워크 설계en_US
dc.title.alternativeA Power Through-Silicon-Via Optimization for Power Delivery Network Design of 3D-ICen_US
dc.typeArticleen_US
dc.relation.page--
dc.contributor.googleauthor이봉기-
dc.contributor.googleauthor정정화-
dc.contributor.googleauthorLee, Bong-Ki-
dc.contributor.googleauthorChong, Jong-Wha-
dc.sector.campusS-
dc.sector.daehakCOLLEGE OF ENGINEERING[S]-
dc.sector.departmentDEPARTMENT OF ELECTRONIC ENGINEERING-
dc.identifier.pidjchong-
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