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COLLEGE OF ENGINEERING[S](공과대학)
ELECTRONIC ENGINEERING(융합전자공학부)
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Results 1-4 of 4 (Search time: 0.001 seconds).
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Issue Date
Title
Author(s)
2014-05
Data and edge decision feedback equalizer with ˃ 1.0-UI timing margin for both data and edge samples
유창식
2014-01
Intra-panel interface with clock-embedded differential signalling for large size digital television
유창식
2014-06
A 1.5-5.0 Gb/s clock and data recovery circuit with dual-PFD phase-rotating phase locked loop
유창식
2014-06
A 100-kS/s 8.3-ENOB 1.7-mu W Time-Domain Analog-to-Digital Converter
유창식
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유창식
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phase rotation
1
serial interface
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speculative DFE
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successive approximation register...
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time-domain comparator
1
wireline transceiver
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