Skew Compensation Technique for Source-Synchronous Parallel DRAM Interface
- Title
- Skew Compensation Technique for Source-Synchronous Parallel DRAM Interface
- Author
- 유창식
- Keywords
- CMOS; delay-locked loop (DLL); interpin skew compensation; parallel interface; synchronous DRAM (SDRAM)
- Issue Date
- 2013-11
- Publisher
- IEEE
- Citation
- IEEE Transactions on VLSI System, 2013, 21(11), P.2155-2159
- Abstract
- The interpin skew among the data and the strobe signals of a source-synchronous parallel DRAM interface is compensated by a simple delay-locked loop, which reuses the circuitry of a normal input data path. With the interpin skew compensation, the printed circuit board traces of the data and the strobe signals are allowed to have unequal length. The prototype implemented in a 0.13-mu m standard CMOS process shows that the interpin skew is reduced to be less than 26 ps for a 3.2-Gb/s/pin x8 parallel interface.
- URI
- https://ieeexplore.ieee.org/document/6389783/
- ISSN
- 1063-8210
- DOI
- 10.1109/TVLSI.2012.2227853
- Appears in Collections:
- COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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