Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 유창식 | - |
dc.date.accessioned | 2018-03-23T00:43:31Z | - |
dc.date.available | 2018-03-23T00:43:31Z | - |
dc.date.issued | 2013-11 | - |
dc.identifier.citation | IEEE Transactions on VLSI System, 2013, 21(11), P.2155-2159 | en_US |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | https://ieeexplore.ieee.org/document/6389783/ | - |
dc.description.abstract | The interpin skew among the data and the strobe signals of a source-synchronous parallel DRAM interface is compensated by a simple delay-locked loop, which reuses the circuitry of a normal input data path. With the interpin skew compensation, the printed circuit board traces of the data and the strobe signals are allowed to have unequal length. The prototype implemented in a 0.13-mu m standard CMOS process shows that the interpin skew is reduced to be less than 26 ps for a 3.2-Gb/s/pin x8 parallel interface. | en_US |
dc.description.sponsorship | This work was supported in part by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by MEST (2010-0012551) and the IT R&D Program of MKE/KEIT (Large-Scale Hyper-MLC SSD Technology Development, under Grant 10035202) of Korea. | en_US |
dc.language.iso | en | en_US |
dc.publisher | IEEE | en_US |
dc.subject | CMOS | en_US |
dc.subject | delay-locked loop (DLL) | en_US |
dc.subject | interpin skew compensation | en_US |
dc.subject | parallel interface | en_US |
dc.subject | synchronous DRAM (SDRAM) | en_US |
dc.title | Skew Compensation Technique for Source-Synchronous Parallel DRAM Interface | en_US |
dc.type | Article | en_US |
dc.relation.volume | 21 | - |
dc.identifier.doi | 10.1109/TVLSI.2012.2227853 | - |
dc.relation.page | 2155-2159 | - |
dc.relation.journal | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.contributor.googleauthor | Lee, Jang-Woo | - |
dc.contributor.googleauthor | Kim, Hong-Jung | - |
dc.contributor.googleauthor | Jeong, Chun-Seok | - |
dc.contributor.googleauthor | Lee, Jae-Jin | - |
dc.contributor.googleauthor | Yoo, Changsik | - |
dc.relation.code | 2013003600 | - |
dc.sector.campus | S | - |
dc.sector.daehak | COLLEGE OF ENGINEERING[S] | - |
dc.sector.department | DEPARTMENT OF ELECTRONIC ENGINEERING | - |
dc.identifier.pid | csyoo | - |
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