Thermal Aware Timing Budget for Buffer Insertion in Early Stage of Physical Design
- Title
- Thermal Aware Timing Budget for Buffer Insertion in Early Stage of Physical Design
- Author
- 정정화
- Keywords
- Buffer insertion; thermal variation; cell delay; library characterization
- Issue Date
- 2012-05
- Publisher
- 대한전자공학회
- Citation
- Journal of semiconductor technology and science, May 2012, P.397-404, 8P.
- Abstract
- Thermal generation by power dissipation of the highly integrated System on Chip (SoC) device is irregularly distributed on the intra chip. It leads to thermal increment of the each thermally different region and effects on the propagation timing; consequently, the timing violation occurs due to the misestimated number of buffers. In this paper, the timing budgeting methodology considering thermal variation which contains buffer insertion with wire segmentation is proposed. Thermal aware LUT modeling for cell intrinsic delay is also proposed. Simulation results show the reduction of the worst delay after implementing thermal aware buffer insertion using by proposed wire segmentation up to 33% in contrast to the original buffer insertion. The error rates are measured by SPICE simulation results.
- URI
- http://koreascience.or.kr/article/ArticleFullRecord.jsp?cn=E1STAN_2012_v12n4_397http://hdl.handle.net/20.500.11754/49899
- ISSN
- 1598-1657; 2233-4866
- DOI
- 10.5573/JSTS.2012.12.4.397
- Appears in Collections:
- COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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