Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 정정화 | - |
dc.date.accessioned | 2018-03-21T01:46:01Z | - |
dc.date.available | 2018-03-21T01:46:01Z | - |
dc.date.issued | 2012-05 | - |
dc.identifier.citation | Journal of semiconductor technology and science, May 2012, P.397-404, 8P. | en_US |
dc.identifier.issn | 1598-1657 | - |
dc.identifier.issn | 2233-4866 | - |
dc.identifier.uri | http://koreascience.or.kr/article/ArticleFullRecord.jsp?cn=E1STAN_2012_v12n4_397 | - |
dc.identifier.uri | http://hdl.handle.net/20.500.11754/49899 | - |
dc.description.abstract | Thermal generation by power dissipation of the highly integrated System on Chip (SoC) device is irregularly distributed on the intra chip. It leads to thermal increment of the each thermally different region and effects on the propagation timing; consequently, the timing violation occurs due to the misestimated number of buffers. In this paper, the timing budgeting methodology considering thermal variation which contains buffer insertion with wire segmentation is proposed. Thermal aware LUT modeling for cell intrinsic delay is also proposed. Simulation results show the reduction of the worst delay after implementing thermal aware buffer insertion using by proposed wire segmentation up to 33% in contrast to the original buffer insertion. The error rates are measured by SPICE simulation results. | en_US |
dc.description.sponsorship | This work was sponsored by ETRI SW-SoC R&BD Center, Human Resource Development Project. This research was also supported by the MKE (The Ministry of Knowledge Economy), Korea, under the ITRC(Information Technology Research Center) support program supervised by the NIPA(National IT Industry Promotion Agency) (NIPA-2012-H0301-12-1011). | en_US |
dc.language.iso | en | en_US |
dc.publisher | 대한전자공학회 | en_US |
dc.subject | Buffer insertion | en_US |
dc.subject | thermal variation | en_US |
dc.subject | cell delay | en_US |
dc.subject | library characterization | en_US |
dc.title | Thermal Aware Timing Budget for Buffer Insertion in Early Stage of Physical Design | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.5573/JSTS.2012.12.4.397 | - |
dc.relation.page | - | - |
dc.contributor.googleauthor | Kim, Min-beom | - |
dc.contributor.googleauthor | Ahn, Byung-Gyu | - |
dc.contributor.googleauthor | Kim, Jae-hwan | - |
dc.contributor.googleauthor | Lee, Bong-ki | - |
dc.contributor.googleauthor | Chong, Jong-wha | - |
dc.sector.campus | S | - |
dc.sector.daehak | COLLEGE OF ENGINEERING[S] | - |
dc.sector.department | DEPARTMENT OF ELECTRONIC ENGINEERING | - |
dc.identifier.pid | jchong | - |
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