Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 추민성 | - |
dc.date.accessioned | 2024-06-26T05:03:41Z | - |
dc.date.available | 2024-06-26T05:03:41Z | - |
dc.date.issued | 2022-12-28 | - |
dc.identifier.citation | IEEE ACCESS, v. 11, page. 7530-7539 | en_US |
dc.identifier.issn | 2169-3536 | en_US |
dc.identifier.uri | https://ieeexplore.ieee.org/document/10002363 | en_US |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/190991 | - |
dc.description.abstract | This paper presents a design automation methodology for ring voltage-controlled oscillators (RVCOs) with their realistic and physical characteristics captured. With multiple sets of input constraints such as target frequency, phase noise, and control voltage range, the proposed algorithm automatically finds the design candidates that satisfy the target constraints, by running iterative post-layout simulations with auto-generated layouts and testbenches. The number of post-layout simulations is significantly reduced by the backtracking algorithm that observes the simulation results and determines the search direction. The proposed algorithm is applied to generate RVCOs in 40-nm planar and 7-nm FinFET technologies for DDR5 applications, and it turns out the proposed methodology produces sets of design parameters that meet the target specification in multiple technologies. | en_US |
dc.description.sponsorship | 10.13039/100004358-Samsung Research Funding and Incubation Center of Samsung Electronics (Grant Number: SRFC-IT2001-02) Institute of Information and Communications Technology Planning and Evaluation (IITP) Grant Korea Government (MSIT) (Development of Multi-Rate, Ultra-High-Speed Links With 100+Gbps Aggregate Bandwidth for AI Computing Platforms) (Grant Number: 2020-0-01307) ITP Grant 10.13039/501100003621-Korea Government (MSIT) (Software Systems for AI Semiconductor Design) (Grant Number: 2021-0-00754) 10.13039/501100003725-National Research Foundation of Korea (NRF) Grant 10.13039/501100003621-Korea Government (MSIT) (Grant Number: RS-2022-00166953 and 2021R1C1C1003634) 10.13039/501100002380-Research Fund of Hanyang University (Grant Number: HY-2022-0981) | en_US |
dc.language | en_US | en_US |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | en_US |
dc.relation.ispartofseries | v. 11;7530-7539 | - |
dc.subject | Ring oscillators | en_US |
dc.subject | design automation | en_US |
dc.subject | layout generation | en_US |
dc.subject | CMOS | en_US |
dc.subject | FinFET | en_US |
dc.subject | frequency control | en_US |
dc.subject | phase noise | en_US |
dc.title | An Automated Design Methodology for Ring Voltage-Controlled Oscillators in Nanometer CMOS Technologies | en_US |
dc.type | Article | en_US |
dc.relation.volume | 11 | - |
dc.identifier.doi | 10.1109/ACCESS.2022.3232960 | en_US |
dc.relation.page | 7530-7539 | - |
dc.relation.journal | IEEE ACCESS | - |
dc.contributor.googleauthor | Lee, Dongjun | - |
dc.contributor.googleauthor | PARK, GIJIN | - |
dc.contributor.googleauthor | HAN, JAEDUK | - |
dc.contributor.googleauthor | CHOO, MIN-SEONG | - |
dc.relation.code | 2022036070 | - |
dc.sector.campus | E | - |
dc.sector.daehak | COLLEGE OF ENGINEERING SCIENCES[E] | - |
dc.sector.department | SCHOOL OF ELECTRICAL ENGINEERING | - |
dc.identifier.pid | mschoo | - |
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