Low-Phase-Noise 20-GHz Phase-Locked Loop Using Harmonic-Tuned VCO Assisting With g(m) -Boosting Technique
- Title
- Low-Phase-Noise 20-GHz Phase-Locked Loop Using Harmonic-Tuned VCO Assisting With g(m) -Boosting Technique
- Author
- 장태환
- Keywords
- 20 GHz; CMOS; frequency synthesizer; LC oscillator; low phase noise; low power; phase-locked loop (PLL); voltage-controlled oscillator (VCO)
- Issue Date
- 2023-10
- Publisher
- Institute of Electrical and Electronics Engineers
- Citation
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v. 31, NO. 10, Page. 1.0-5.0
- Abstract
- In this study, we present a low-phase-noise 20-GHz phase locked loop (PLL) with simultaneous gm-boosted and third-harmonic impedance-tuned voltage-controlled oscillator (VCO). The proposed PLL is implemented using the 65-nm CMOS technology. By both implementing a cross-coupled center-tapped inductor and controlling the harmonic impedance, the phase noise is improved by approximately 3.4 dB. An auxiliary cross-coupled pair (CCP) is used to boost the transconductance, while a parallel quarter-wave open stub is added to minimize the second-harmonic impedance for the output signal as the squared waveform. The proposed PLL demonstrated a measured phase noise of - 102.05 dBc/Hz at a 1-MHz offset frequency. Based on the measured phase noise, the proposed PLL can achieve a figure of merit (FOM) of - 174.35 dBc/Hz, while it consumes 23.6 mW with a supply voltage of 1 V.
- URI
- https://ieeexplore.ieee.org/document/10190110https://repository.hanyang.ac.kr/handle/20.500.11754/187683
- ISSN
- 1063-8210;1557-9999
- DOI
- 10.1109/TVLSI.2023.3294404
- Appears in Collections:
- COLLEGE OF ENGINEERING SCIENCES[E](공학대학) > ELECTRICAL ENGINEERING(전자공학부) > Articles
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