Design of n(+)-base width of two-terminal-electrode vertical thyristor for cross-point memory cell without selector
- Title
- Design of n(+)-base width of two-terminal-electrode vertical thyristor for cross-point memory cell without selector
- Author
- 박재근
- Keywords
- thyristor; cross-point memory; half-bias scheme; endurance; power consumption
- Issue Date
- 2021-01
- Publisher
- IOP PUBLISHING LTD
- Citation
- NANOTECHNOLOGY, v. 32, NO 14, article no. 14LT01
- Abstract
- The n+-base width of a two-terminal vertical thyristor fabricated with n++(top-emitter)-p+(base)-n+(base)-p++(bottom-emitter) epitaxial Si layers was designed to produce a cross-point memory cell without a selector. Both the latch-up and latch-down voltages increased linearly with the n+-base width, but the voltage increase slope of the latch-up was 2.6 times higher than that of the latch-down, and the memory window increased linearly with the n+-base width. There was an optimal n+-base width that satisfied cross-point memory cell operation; i.e. ∼180 nm, determined by confirming that the memory window principally determined the condition of operation as a cross-point memory cell (i.e. one half of the latch-up voltage being less than the latch-down voltage and a sufficient voltage difference existing between the latch-up and latch-down voltages). The vertical thyristor designed with the optimal n+-base width produced write/erase endurance cycles of ∼109 by sustaining a memory margin (Ion/Ioff) of 102, and the cross-point memory cell array size of 1024 K sustained a sensing margin of 99 %, which is comparable with that of current dynamic random-access memory (DRAM). In addition, in the cross-point memory cell array, a ½ bias scheme (i.e. a memory array size of 1024 K for 0.02 W of power consumption) resulted in lower power consumption than a $1/3$ bias scheme (i.e. a memory array size of 256 K for 0.02 W of power consumption).
- URI
- https://iopscience.iop.org/article/10.1088/1361-6528/abd357https://repository.hanyang.ac.kr/handle/20.500.11754/175586
- ISSN
- 0957-4484 ; 1361-6528
- DOI
- 10.1088/1361-6528/abd357
- Appears in Collections:
- COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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