Improved Neutral-Point Voltage Balancing Control With Time Delay Compensation and Antiwindup Loop for a Three-Level NPC Inverter

Abstract

This article proposes an improved neutral-point voltage balancing control (NPVBC) with time delay compensation and an antiwindup loop based on a dynamic change limit for a three-level neutral-point clamped (NPC) voltage-source inverter. NPVBC is essential for a three-level NPC inverter since it has a separate dc link. In an NPVBC based on the carrier-based pulsewidth modulation (CBPWM), the neutral-point (NP) voltage is regulated by synthesizing the NP current. The conventional NP voltage balancing controller is designed as a proportional–integral controller; however, time delays due to the digital control and pulsewidth modulation, and antiwindup loop were not considered despite the fact that digital control delay disturbs the accurate synthesis of NP current and the windup phenomenon may appear on the regulator since synthesizable NP current range can be limited by operating condition. To solve these problems, this article proposes improvement methods for NPVBC with digital delay compensation and an antiwindup loop based on CBPWM. Analysis on the effect of digital delay is described, and the time delays compensation method is proposed. Furthermore, an NP voltage balancing controller with an antiwindup loop is proposed along with an analysis of the synthesizable NP current range. With the proposed method, NP voltage ripples can be reduced, and control stability of the NPVBC can be greatly improved by preventing the windup phenomenon that may occur when the inverter output is insufficient. To verify the proposed methods, simulations and experiments, including elevator tower test, were conducted, and the results verify the effectiveness of the proposed methods.