Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 박성주 | - |
dc.date.accessioned | 2021-03-31T04:20:15Z | - |
dc.date.available | 2021-03-31T04:20:15Z | - |
dc.date.issued | 2001-11 | - |
dc.identifier.citation | 대한전자공학회 기타 간행물, v. 1, page. 137-142 | en_US |
dc.identifier.uri | https://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE02012649? | - |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/161039 | - |
dc.description.abstract | For a System-on-a-Chip(SoC) comprised of multiple IP cores with IEEE 1149.1 boundary scan design, various design techniques have been proposed to provide diverse test link configurations. In this paper, we present a new design of Wrapped Core Linking Module(WCLM) that enables systematic integration of 1149.1 JTAG'd cores and PI500 wrapped cores. The design preserves compatibility with standards and scalablity for hierarchical access. | en_US |
dc.language.iso | en_US | en_US |
dc.publisher | 대한전자공학회 | en_US |
dc.title | A New Wrapped Core Linking Module for SoC Testing | en_US |
dc.type | Article | en_US |
dc.relation.journal | 전자공학회논문지 | - |
dc.contributor.googleauthor | Song, Jaehoon | - |
dc.contributor.googleauthor | Yi, Hyunbin | - |
dc.contributor.googleauthor | Yang, JoonSik | - |
dc.contributor.googleauthor | Park, Sungju | - |
dc.relation.code | 2012101087 | - |
dc.sector.campus | E | - |
dc.sector.daehak | COLLEGE OF COMPUTING[E] | - |
dc.sector.department | DIVISION OF COMPUTER SCIENCE | - |
dc.identifier.pid | paksj | - |
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