Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 박성주 | - |
dc.date.accessioned | 2020-08-10T06:44:48Z | - |
dc.date.available | 2020-08-10T06:44:48Z | - |
dc.date.issued | 2004-10 | - |
dc.identifier.citation | ISOCC 2004 Conference, Page. 506-509 | en_US |
dc.identifier.uri | https://dbpia.co.kr/journal/articleDetail?nodeId=NODE01810825 | - |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/152141 | - |
dc.description.abstract | For a System-on-a-Chip(SoC) comprised of multiple IP cores, various design techniques have been proposed to provide diverse test link configurations for wrapper and scan chains. In this paper, a simple test access mechanism is introduced, where scan chains are efficiently reconfigured. An SoC comprising of interactive and non-interactive mega-cores of various scan architectures can be effectively tested with this mechanism. Design experiments show that functionality, compatability, scalability, and area overhead of our technique are highly competitive to the current state-of art techniques. | en_US |
dc.language.iso | en_US | en_US |
dc.publisher | 대한전자공학회 | en_US |
dc.subject | P1500 Wrapper | en_US |
dc.subject | TAM(Test Access Mechanism) | en_US |
dc.subject | Scan Design | en_US |
dc.title | A Reconfigurable Test Access Mechanism for Embedded Core Test | en_US |
dc.type | Article | en_US |
dc.contributor.googleauthor | Yeom, Kyeongwon | - |
dc.contributor.googleauthor | Min, Piljae | - |
dc.contributor.googleauthor | Song, Jaehoon | - |
dc.contributor.googleauthor | Park, Sungju | - |
dc.sector.campus | E | - |
dc.sector.daehak | COLLEGE OF COMPUTING[E] | - |
dc.sector.department | DIVISION OF COMPUTER SCIENCE | - |
dc.identifier.pid | paksj | - |
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